Design Engineering Director

Cadence Design Systems

4.4

(53)

San Jose, CA

Why you should apply for a job to Cadence Design Systems:

  • 4.4/5 in overall job satisfaction
  • 4.4/5 in supportive management
  • 87% say women are treated fairly and equally to men
  • 89% would recommend this company to other women
  • 87% say the CEO supports gender diversity
  • Ratings are based on anonymous reviews by Fairygodboss members.
  • Parental leave is available for both paternity and maternity
  • Flexible work options available
  • 88% of employees at Cadence say it is a great place to work compared to 57% of employees at a typical U.S.-based company.
  • #R49264

    Position summary

    , Systems Interop and Compliance testing.
    • 2-3 years of management experience leading/mentoring a small team of engineers
    • Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/PCIe/CXL/UCIe/
    • Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.

    • Proficient with Ethernet, PCIe, UCIe standards and Protocols. Proven experience to interpret the standard's specification to develop Electrical and Protocol, Interoperability and Compliance test suites to validate the silicon.

    • Ability to isolate the PHY and controller (MAC/PCS) features to test, develop calibration / compliance lab suites and characterize.

    • Architect and design Printed circuit boards in Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and Power integrity checks / analysis and fixes needed to meet the performance requirements.

    • Experience in PCIe/UCIe LTSSM states / UCIe Interfaces / Ethernet standards is a plus.

    • Proven experience in developing lab automation scripts and test result analysis to debug and root cause silicon failures.

    • Expertise in developing ESD/Latchup/ HTOL tests to meet industry standards reliability qualification & specification

    • Expert level knowledge in Verilog RTL coding for FPGA, python,C/C++

    The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
    We're doing work that matters. Help us solve what others can't.

    Why you should apply for a job to Cadence Design Systems:

  • 4.4/5 in overall job satisfaction
  • 4.4/5 in supportive management
  • 87% say women are treated fairly and equally to men
  • 89% would recommend this company to other women
  • 87% say the CEO supports gender diversity
  • Ratings are based on anonymous reviews by Fairygodboss members.
  • Parental leave is available for both paternity and maternity
  • Flexible work options available
  • 88% of employees at Cadence say it is a great place to work compared to 57% of employees at a typical U.S.-based company.