#R46469
tem Design Enablement team at Cadence in Europe, the Digital Design and Verification Engineer will work closely with SoC architects and senior engineers, deploying Cadence technology in demanding customer projects, creating leading edge MPSoCs for automotive, networking, and consumer markets.
The candidate should have:
Degree in Electrical Engineering or Computer Science
Good understanding of digital design flows from Spec2Gates
Excellent knowledge of hardware and verification languages (e.g., SV, Verilog, VHDL, SystemC)
10 years of experience with state-of-art RTL design & synthesis tools, and state-of-art verification approaches and tools (e.g., UVM, MDV, formal approaches, software-driven verification, vManager, CocoTB)
Strong motivation to learn quickly Cadence verification tools, flows and methodologies
Working knowledge of UNIX/Linux, shells, programming and scripting (Perl, TCL, Python)
Good communication skills and ability to work remotely
Team player (fluent in English)
Willingness to travel across Europe and work with customers
Additional Information:
Must be EU national or eligible to work in Poland
Check what we can offer you:
Competitive salary package adequate to competencies
Flexible working hours
Work from office, from home or hybrid
Continuous professional development: trainings and seminars
Possibility to cooperate with people from around the world in an expanding global organization
Employee Stock Purchase Plan, bonuses and stocks
Private medical care
Life insurance
Multisport Plus cards
Social Fund benefits
Recommendation bonuses & Internal recognition program
Additional paid days off - Recharge days, Volunteer Time Off
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