DSP or Serdes (Viterbi and encoder design) RTL Senior Principal Digital Design Engineer

Cadence Design Systems

4.4

(53)

San Jose, CA

Why you should apply for a job to Cadence Design Systems:

  • 4.4/5 in overall job satisfaction
  • 4.4/5 in supportive management
  • 87% say women are treated fairly and equally to men
  • 89% would recommend this company to other women
  • 87% say the CEO supports gender diversity
  • Ratings are based on anonymous reviews by Fairygodboss members.
  • Parental leave is available for both paternity and maternity
  • Flexible work options available
  • 88% of employees at Cadence say it is a great place to work compared to 57% of employees at a typical U.S.-based company.
  • #R43530

    Position summary

    s**

    This team is focused on DSP or High Speed Serdes (Viterbi and encoder design). . The ideal candidate will have at least 5 plus years of actual work experience in SerDes as well as a thorough understanding of the end-to-end digital design flow in order to accurately and efficiently collaborate with all members of the technical staff, both analog and digital, regarding overall project development progress and status. This includes but is not limited to:

    • Digital microarchitecture definition and documentation

    • RTL logic design, debug and functional verification

    • IP integration and verification

    • Familiar with the PMA/PMD/PCS layers of the Ethernet protocol is a plus.

    • Understanding of digital architecture trade-offs for power, performance, and area

    • Understanding of proper handling of multiple asynchronous clock domains and their crossings

    • Understanding of Lint checks and proper resolution of errors

    • Understanding synthesis timing constraints, static timing analysis and constraint development

    • Understanding of fundamental physical design flows and stages

    • Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow.

    • Exhibit excellent communication skills and be self-motivated and well organized.

    • Experience with FPGA and/or emulation platform is a plus.

    • Firmware development of embedded microcontroller systems is a plus.

    Substantial experience with Verilog is required, as are excellent logic and debug skills. Engineering expertise in mixed-signal IP development procedures and Ethernet connectivity protocol knowledge are also strongly preferred.

    #LI-MA1

    The annual salary range for California is $150,500 to $279,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
    We're doing work that matters. Help us solve what others can't.

    Why you should apply for a job to Cadence Design Systems:

  • 4.4/5 in overall job satisfaction
  • 4.4/5 in supportive management
  • 87% say women are treated fairly and equally to men
  • 89% would recommend this company to other women
  • 87% say the CEO supports gender diversity
  • Ratings are based on anonymous reviews by Fairygodboss members.
  • Parental leave is available for both paternity and maternity
  • Flexible work options available
  • 88% of employees at Cadence say it is a great place to work compared to 57% of employees at a typical U.S.-based company.