Emulation Design Engineer

Cadence Design Systems

4.4

(53)

Shanghai, China

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Position summary

ilities:**

Lead the design and deployment of Emulation PHY logic and models for platforms including Palladium and Protium.
Optimize designs for multi-clock domain synchronization, area, and performance, with a focus on accuracy vs. runtime trade-offs.
Develop and maintain end-to-end verification environments, encompassing:

System-level models including microcontrollers, memories, NoC (Network-on-Chip), and high-speed communication interface Test case generation Interface Circuit Performance Analysis

Contribute to system prototyping for early bring-up and validation of full-system designs.
Collaborate with cross-functional teams to ensure seamless integration from simulation to emulation.
Drive innovation in emulatable IP solutions and contribute to the evolution of verification methodologies.

Required Qualifications:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
Experience of 5-16 years. Multiple positions available.
Strong experience with system-level design and communication standards such as: PCIe, UCIe, Ethernet, UALink, DDR, USB, SPI, JTAG, AMBA protocols
Proficiency in:

SystemVerilog for synthesizable RTL design C and Python for modeling,scripting, and automation Converting Analog Mixed Signal Designs logic to emulation compatible models maintaining functional and bit accuracy, and enabling software stack development for configuration, control and status monitoring Debug and test case development

Hands-on experience with emulation platforms: Palladium, Protium, Zebu, HAPS, Veloci, FPGA
Deep understanding of verification flows and emulation acceleration techniques

Preferred Skills:

Experience building emulatable AVIP solutions
Familiarity with end-to-end verification environments from simulation through emulation
Experience in system prototyping and bring-up
Strong analytical and problem-solving skills
Excellent communication and leadership abilities

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