Hardware Design for Advanced Technologies

coarse granularity level (memory or functional blocks), allowing the use of the existing place & route engines, modified to understand different types of 3D interfaces in different tool sessions. Obviously, much finer system partitioning at die level, involving multiple active layers can't benefit from the above-mentioned methods & tools. Further, multi-layered dies can be stacked to create 3D chiplets that will be integrated in multi-die packages causing significant increase of the design space size. The use of state-of-the-art 3D enabled place & route, power, and thermal simulation tools to explore different architecture parameters, technology options and partitioning strategies is out of the question due to complex set-up and run-time for reasonably sized designs.

Problem definition

Having in mind the technology assumptions above, EDA for future ICs should bridge the gap at two levels. First, enablement of multiple active layers for place & route and sign-off tools, such as introduction of the active back side. Second, additional high-level tools will be required for design planning to enable early holistic design analysis for performance, power, area, cost, and temperature (PPACT). On top of EDA enablement, there is also a fundamental question on how all the above will impact system architecture design, including complete memory hierarchy.

Thesis objectives

Together with Cadence R&D team, the candidate will work on physical design enablement (place & route) of the active back-side, starting with the correct understanding and formulation of the technology specifications. Design enablement per se will include the development of appropriate algorithms and methods implemented on top of the existing place & route tool. These will be then used for system-level characterization, first at block and then eventually at SoC level. The analysis will be carried out to capture system architecture-technology trade-offs. Further, the candidate will work on high-level exploration framework based on 3Dblox standard. The objective here is to enable System Technology Co-optimization early in the design cycle. The emphasis here is less on the design flow enablement and more on the interaction between system architecture design, 2D/3D technology (including active back-side) & partitioning choices. For example, the candidate will study & characterize data movements in complex SoCs assuming current & future 5.5D technology options with tuneable communication and memory specifications to propose up to date energy, delay & latency envelopes of future systems.

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