Lead Application Engineer

Cadence Design Systems

4.4

(53)

Shenzhen, China

Why you should apply for a job to Cadence Design Systems:

  • 4.4/5 in overall job satisfaction
  • 4.4/5 in supportive management
  • 87% say women are treated fairly and equally to men
  • 89% would recommend this company to other women
  • 87% say the CEO supports gender diversity
  • Ratings are based on anonymous reviews by Fairygodboss members.
  • Parental leave is available for both paternity and maternity
  • Flexible work options available
  • 88% of employees at Cadence say it is a great place to work compared to 57% of employees at a typical U.S.-based company.
  • #R26781

    Position summary

    n the following areas:

    1. 2.Design experience in Verilog/VHDL for IP or SoC chip level.
    2. HW verification with knowledge of System Verilog/VHDL and HDL simulators
    3. FPGA prototyping project experience
    4. Experience with hardware emulator or accelerator is a big advantage
    5. Advanced Verification Methodology like UVM is a plus
    6. Knowledge of Unix and Linux is highly desired
    7. Strong verbal and written communication skills in English
    8. Strong teamwork skills with good human relationship
      We're doing work that matters. Help us solve what others can't.

    Why you should apply for a job to Cadence Design Systems:

  • 4.4/5 in overall job satisfaction
  • 4.4/5 in supportive management
  • 87% say women are treated fairly and equally to men
  • 89% would recommend this company to other women
  • 87% say the CEO supports gender diversity
  • Ratings are based on anonymous reviews by Fairygodboss members.
  • Parental leave is available for both paternity and maternity
  • Flexible work options available
  • 88% of employees at Cadence say it is a great place to work compared to 57% of employees at a typical U.S.-based company.