Lead Applications Engineer - DDR Design IP

Cadence Design Systems

4.4

(53)

San Jose, CA

Why you should apply for a job to Cadence Design Systems:

  • 4.4/5 in overall job satisfaction
  • 4.4/5 in supportive management
  • 87% say women are treated fairly and equally to men
  • 89% would recommend this company to other women
  • 87% say the CEO supports gender diversity
  • Ratings are based on anonymous reviews by Fairygodboss members.
  • Parental leave is available for both paternity and maternity
  • Flexible work options available
  • 88% of employees at Cadence say it is a great place to work compared to 57% of employees at a typical U.S.-based company.
  • #R51279

    Position summary

    esales Engineer, you will use your knowledge of different memory interface standards to architect memory solutions for customers using Cadence DDR IP. This role offers the benefit of both technical growth and business skill development. You will be part of the Technical Field Organization helping educate customers and providing solutions using our DDR IP portfolio. Our memory PHY and controller IPs are used in data centers, mobile devices, automobiles and consumer devices

    Responsibilities include:

    • Technical presales of Memory IP

    • Present Cadence's IP portfolio and capabilities to prospective customers

    • Work closely with IP Sales staff, marketing and R&D teams to win opportunities

    • Performance evaluations of Cadence memory IP and development of related infrastructure

    • Serve as a product expert in memory controller and PHY IPs and protocols

    • Provide quick-turn product specific technical support to customers, field teams, definers and designers

    • Write application notes, user guides, articles, design ideas, new product proposals, and evaluation kit manuscripts for internal and/or external publication

    • Travel to customer sites may be required occasionally

    Qualifications:

    • BS in EE, CE or related equivalent with 5+ years of work experience or MS in EE, CE or equivalent with 3+ year of work experience

    • Knowledge of one or more DRAM protocols - DDR4/5, LPDDR4/5/5X, HBM2/3, GDDR6

    • Experience with simulation and synthesis tools

    • Strong knowledge of ASIC flow, RTL/Verilog

    • Individual leadership and initiative to manage pre-sales accounts

    • Excellent presentation skills and verbal/written communication skills is a must

    Nice to have:

    • Experience on memory subsystem verification and/or performance analysis

    • Knowledge of System Verilog and FPGA design

    • Knowledge of AXI, DFI and MIPI protocols

    • Working knowledge of memory controller and memory PHY

    The annual salary range for California is $102,900 to $191,100. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
    We're doing work that matters. Help us solve what others can't.

    Why you should apply for a job to Cadence Design Systems:

  • 4.4/5 in overall job satisfaction
  • 4.4/5 in supportive management
  • 87% say women are treated fairly and equally to men
  • 89% would recommend this company to other women
  • 87% say the CEO supports gender diversity
  • Ratings are based on anonymous reviews by Fairygodboss members.
  • Parental leave is available for both paternity and maternity
  • Flexible work options available
  • 88% of employees at Cadence say it is a great place to work compared to 57% of employees at a typical U.S.-based company.