Lead Design Engineer

cal Design teams in multiple successful ASIC/IP tapeouts.

Strong ability on RTL debug , and logic development.

Knowledge of the IP/SoC level timing closure flow and methodology.

Strong command of synthesis, STA, design for test, and design methodologies

Ability to handle multiple projects/tasks successfully

Experience in IP/ASIC timing constraints generation and timing closure.

Strong background in Constraint analysis and debug, using industry standard tools.

Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and Bist testing.

Team player with a passion to innovate and can-do attitude.

Self-starter and highly motivated.

Desired skills

Knowledge of DDR/GDDR DRAM protocol; high-speed PHYs

Experience designing or integrating IP

Experience in high speed and low power digital design using advanced deep micron process.

Experience with highly configurable designs
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