#R48480
ce in ASIC design environment
Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification
Experience with Cadence digital design tools will be an added advantage
Hands on scripting languages like Python, Perl, TCL, Unix shell etc
Strong understanding of digital logic design, processor design, and computer architecture is desirable
Should have excellent communication, analytical and problem solving skills
Should be self-motivated and good team player
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