Lead Solutions Engineer - Runset Enablement (Physical Verification)

ovements.

• Provide technical enablement and support for customers on tool usage and advanced methodologies.

• Mentor junior engineers and establish best practices for runset development and QA.

• Work closely with internal teams to ensure timely delivery of verification solutions.

Qualifications

• MS degree with 5+ years of experience or PhD with 3+ years in Electrical Engineering, Computer Science, or related field.

• Strong understanding of semiconductor design and physical verification flows.

Experience and Technical Skills

• Proven expertise in developing and validating DRC and LVS runsets for Pegasus or similar tools (Calibre, ICV, Assura).

• Good-to-have: Experience with PERC and Fill runsets.

• Deep knowledge of advanced process technologies and methodologies (Ground Rules, SmartFill, ESD).

• Proficiency in scripting languages (TCL, Python, Perl) and Linux/Unix environments.

• Familiarity with chip fabrication processes and multi-die integration challenges.

• Experience in automation frameworks for regression and validation.

Behavioral Skills

• Strong leadership and mentoring capabilities.

• Excellent written, verbal, and presentation skills.

• Ability to influence cross-functional teams and drive strategic initiatives.

• Innovative mindset to explore unconventional solutions and optimize workflows.

• Operate with integrity and foster collaboration across global teams.

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

We're doing work that matters. Help us solve what others can't.