#R48152
n Requirements:
Bachelor or above degree in majors of EE/CS/IT, with 5+ years work experience
Extensive knowledge of the design rule for the process of N7/N5 and below
Knowledge of scripting languages and use in methodology
Ability of fixing the physical design violations, including: DRC, DFM, LVS, ANT, ERC etc.
Deep experience of static timing analysis
Ability to learn quickly
High level of communication and teamwork
Carefulness, responsibility, and persistence
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