Principal Application Engineer

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Job Overview:

This position has the exciting challenge of being part of a growing team of Digital Back End Engineers that enable customers to implement design with Cadence tools.

Job Responsibilities:

• Understanding of Digital microarchitecture definition and documentation

• Understanding of RTL logic design, debug and functional verification

• Understanding of IP integration and verification

• Understanding of digital architecture trade-offs for power, performance, and area

• Understanding of proper handling of multiple asynchronous clock domains and their crossings

• Understanding of synthesis timing constraints, static timing analysis and constraint development

• Understanding of fundamental physical design flows, e.g. floor planning and clock tree synthesis

• Understanding of the impacts of Analog and mixed-signal design and verification on digital-on-top development flow.

• Understanding of functional ECO flow and conformal ECO

• Experience with FPGA and/or emulation platform

• Firmware development of embedded microcontroller systems is a plus.

• Substantial experience with Verilog is required, as are excellent logic and debug skills.

Job Qualifications:

• Minimum 5 years of ASIC backend design experience.

• Must have gone through successful tapeouts in advance technology nodes

Additional Skills/Preferences:

• Be self-motivated and well organized.

Additional Information:

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

Travel: >10%
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