Principal Application Engineer - Design Verification
Yokohama, Japan
Why you should apply for a job to Cadence Design Systems:
Ranked as one of the Best Tech Companies for Women in 2022
4.4/5 in overall job satisfaction
4.4/5 in supportive management
87% say women are treated fairly and equally to men
89% would recommend this company to other women
87% say the CEO supports gender diversity
Parental leave is available for both paternity and maternity
Flexible work options available
88% of employees at Cadence say it is a great place to work compared to 57% of employees at a typical U.S.-based company.
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Position summary
ign experience in Verilog/VHDL for IP or SoC chip level.
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Verification with knowledge of System Verilog/VHDL and HDL simulators.
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Experience of using formal verification, JasperGold experience is a plus.
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Advanced Verification Methodology like UVM is a plus.
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Strong verbal and written communication skills in Japanese is needed.
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Business-level English proficiency is preferred.
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Strong teamwork skills with good human relationship.
We're doing work that matters. Help us solve what others can't.
Why you should apply for a job to Cadence Design Systems:
Ranked as one of the Best Tech Companies for Women in 2022
4.4/5 in overall job satisfaction
4.4/5 in supportive management
87% say women are treated fairly and equally to men
89% would recommend this company to other women
87% say the CEO supports gender diversity
Parental leave is available for both paternity and maternity
Flexible work options available
88% of employees at Cadence say it is a great place to work compared to 57% of employees at a typical U.S.-based company.