Principal Customer Engagement Engineer - Xcelium

Cadence Design Systems

4.4

South Korea

Ranked as one of the Best Tech Companies for Women in 2022

4.4/5 in overall job satisfaction

4.4/5 in supportive management

87% say women are treated fairly and equally to men

89% would recommend this company to other women

87% say the CEO supports gender diversity

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Parental leave is available for both paternity and maternity

Flexible work options available

88% of employees at Cadence say it is a great place to work compared to 57% of employees at a typical U.S.-based company.

#R48583

f CS or EE with 10+ years of industry experience.

Minimum 10 years hands-on, high expertise on hardware design & verification techniques.
Hands on experience using HDL simulator (e.g. ies, vcs or questa, but ies preferred) is a must.
Experience of RTL design or verification with Verilog / SV Language or C/C++ or System C.
Understanding standard BUS protocol like AMBA or interface protocol.
Hands on Verification experience using SystemVerilog/Verilog/VHDL/SystemC.
Experience on UVM methodology or similar one should be preferred.
Hands on Design experience using SystemVerilog, Verilog and VHDL.
Knowledge of VIPs, and code & functional coverage tools (IMC preferred) and technologies.
Knowledge of Metric Driven Verification (MDV) using vManager CS should be preferred.
Hands-on experience optimizing RTL, Gate-level simulation for improving performance by using standard profiling tools is a big plus.
Good communication skills in English and a strong desire for working in a global environment with customers and BU people.

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