Principal Design Engineer

Cadence Design Systems

4.4

Pune, India

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chitectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices

Develop synthetic memory traffic/traces that are representative of real-world applications (CPU, GPU, DSP, NoC, etc)
Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks

Required Skills

BE/B.Tech ME/M.Tech in ECE, E&TC, CS or similar
8+ years of experience in hardware modeling, functional or performance
Strong coding skills in C++, SystemC and Transaction Level Modeling (TLM)
Basic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs

Additional Skills

Understand RTL-Verilog, SV, UVM and experience analyzing waveforms
Understand memory protocols and timing - DDR4, DDR5, LP4, LP5
Experience using performance simulators - Memory Controller, NoC, CPU models
Coding in Python and familiarity with packages like Pandas, Matplotlib
Experience working with performance benchmarks - SPEC, STREAM, etc
Concepts related to Quality of Service (QoS) and how memory controller can tradeoff performance and latencies

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