Principal Design Engineer

Controller and PHY IP solution of Cadence.

• The work involved will be working with the existing functional verification environment, addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions, supporting customers in case of any issues with using the verification environment, and functional and code coverage.

• As a part of delivery criteria, the engineer would need to provide Demosim testbench with standard test patterns that aid as a reference for customer for seamless integration of our IP's.

• The engineer would be responsible to ensure that the design is in line with the technical and quality requirements set for the team - particularly with respect to functional and code coverage.

• Participate in technical discussions and represent verification team in all the discussions with internal and external customers.

• Review all technical deliverables from team members and guide team members to meet quality and the schedule.

• Fully accountable for quality design verification as per the schedule.

• Track the verification progress, identify potential risks, and mitigation plan.

• Mentor and provide technical guidance to team working in the projects.

• Contribute to verification process and methodology improvements to boost efficiency and productivity.

Position Requirements:

• BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.

• 8+ years of Design Verification experience with SV/UVM

• Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.

• Design Verification experience verifying complex designs and leading projects from concept to verification closure.

• Should have knowledge on all aspects of verification components & verification metrics.

• Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.

• Prior RTL Design experience using Verilog is a must - so that the verification engineer is self-sufficient for most aspects of debugging.

• Prior experience in IP verification of memory IP (DDR/HBM/LPDDR) would be an added advantage.

Behavioral skills required:

• Must possess strong written, verbal and presentation skills.
• Good communication and interpersonal skills, demonstrate teamwork and collaboration skills.
• Ability to establish a close working relationship with both customer peers and management.
• Explore what's possible to get the job done, including creative use of unconventional solutions
• Work effectively across functions and geographies
• Push to raise the bar while always operating with integrity

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