afety certification.
Required Skills and Experience:
- 8-10 years of design verification experience
- BS (or higher) in EE/Computer Engineering
- Experience in leading a small team
- Excellent knowledge of computer architecture/micro-architecture and design verification fundamentals
- Expertise with Verilog and popular EDA simulation, SystemVerilog assertions and functional coverage
- Good working knowledge of scripting languages like Perl, Unix shell or similar languages
- Knowledge of technical safety concepts and requirement specifications according to ISO 26262
- Proficient with C language and assembly language
- Excellent written and oral communication skills necessary
- Exposure to debugging netlist/gate level simulation.
- General understanding OS.
- Exposure to MISRA coding guidelines
- Experience in fault simulation tools and methodologies
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