Principal Design Engineer - Memory Modeling Portfolio

ry IP as well as in developing and using lifecycle processes to ensure product quality.

• Must be able to analyze customer & vendor protocol requirements and execute on complex projects from requirement to delivery to post-delivery support

• Communication & collaboration with peers & internal partners as well as strong individual/independent R&D skills are required.

• Regular field AE & external customer interaction and representing Cadence to external customers is required for support of memory models. Must be able to facilitate discussions with AE & customer.

• Ability to mentor less experienced engineers &/or participate in cross-functional projects

• Must participate in team processes as well as evaluate and recommend process improvements.

Required Experience:

• The position requires BSEE with at least 7 yrs of industry experience in designing hardware systems OR a MSEE with at least 5 years of experience in designing hardware systems

• Must have excellent communication skills with both written and spoken English.

• Expert level knowledge of RTL design using languages Verilog/SystemVerilog is required along with experience using RTL verification tools and flows.

• Debugging experience.

• Experience with team-wide collaboration tools and process.

• Drive and ability to schedule workload and plan own tasks effectively.

Strongly recommended:

• Verification experience using Cadence simulation and/or emulation products is highly desired. Programming experience with scripting languages like Perl, TCL, C-shell is strongly recommended.
• Verification experience using UVM test environments is highly desired.
• Experience in memory sub-system design and operation is strongly recommended.

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