Principal FPGA Design Engineer

, documentation and releasing the IPs to end users;

• Working on FPGA IP Design, Verification/Simulation, Timing closure, Validation of IP on the hardware;

• Enhancing current IPs as well as developing new IPs.

• Debug and fix internal regression failures for FPGA IPs.

• Documentation of IPs

The ideal candidate will have the following skills and experience:

• Master degree in Electrical Engineering with 5+ years of experience

• Experience with FPGA design and verification using Verilog

• Experience with high end Xilinx(AMD) FPGAs including using Vivado tool for simulation, Place and route

• Experience in debugging FPGAs in the lab using Vivado hardware manager, debugging with firmware/software

• Experience using Linux servers, Script development using Shell/Perl/TCL

• Experience using Cadence Simulators Incisive or Xcelium

• Detailed knowledge about industry standard interfaces such as PCI Express, DRAM/DDR4, SRAM, I2C, JTAG, AXI

The annual salary range for California is $131,600 to $244,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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