#R51009
This position gives abundant exposure to working on and influencing the latest design styles and verification methodologies used by large semiconductor companies. It may occasionally involve worldwide travel to attend meetings or conferences or to assist with product demonstrations, evaluations, and competitive benchmarks at customer sites.
Desired Technical Skills and Experience
The candidate should possess a BE/B.Tech engineering or higher degree in CS or EE with a minimum 10 years of industry experience.
Minimum of 4 years hands-on experience in applying formal property verification technologies and methodologies.
Hands-on design experience using Verilog, System Verilog is a must.
Hands-on experience with any of the common scripting languages, such as TCL, Perl, Python, etc., is a must.
Desire/Ability to learn complex arithmetic algorithms is a must.
Hands-on Jasper experience is a plus.
Knowledge of arithmetic algorithms (various multiplier implementations like Booth, compression schemes, dividers like SRT, floating point operations) is a plus.
Working knowledge of C++ is a plus.
Hands-on experience with formal software verification is a plus.
Hands-on experience using HDL simulator is a plus.
Knowledge of sign-off methodologies using code & functional coverage is a plus.
Desired Soft Skills and Experience
Highly organized, self-motivated individual with demonstrated ability to multitask
Very good communication skills and a strong desire to work in a global environment with customers, developers, marketing, and sales.
Passionate about adopting and promoting new technologies and making customers successful.
Successful in building and delivering training content on rolling out new products/methodologies.
Highly technical & hands on engineer with an ability to partner with key customers and provide expert support to field application engineers.
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