Principal Software Engineer

e both code and functional coverage, and close coverage gaps

• Develop and use unit level test benches that use functional tests as well as constrained random stimulus.

• When needed, define and develop formal verification environment

Skills

• BS or MS in EE, CS or related engineering discipline

• 5-10 years of demonstrated experience in verification of IPs, Digital Design and SoCs

• Strong experience in design and verification standards and methodologies (SVA, UVM/OVM).

• In-depth knowledge of Verilog and System Verilog HDL and experience with simulators and waveform debugging tools

• Solid understanding and experience with verification of Digital Design and SoC architectures including test planning, constrained random test generation, test stimulus, code coverage, functional coverage.

• A thorough understanding of the high-level verification flow methodology (test plan generation, test generation, failure analysis, coverage analysis and closure).

• Strong experience creating test benches and automating regression test suites, preparing, and presenting detailed verification reviews

• Knowledge of state-of-the-art EDA tools (e.g., Cadence Xcelium...)

• Experience with formal verification is plus.

• Programming experience in languages common to the industry (e.g., C, C++, Shell scripting)

• Solid scripting skills (Python preferred or Perl or TCL).

• Knowledge of test and DFT **(**Scan insertion, Scan compression, test coverage analysis, ATPG pattern generation, simulation and debug, IEEE 1149.1, 1500 and 1687 standards)

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