Product Validation Engineer II

Cadence Design Systems

4.4

(53)

Noida, India

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Position summary

dation Engineer on insertion and validation of DFT technologies such as 1500 Wrapper, Compression, RTL DFT, Low Pin Count Test, Hierarchical Test, LBIST etc. using Cadence Synthesis tool Genus and ATPG using Cadence Test tool Modus on in-house and customer designs.

Create testplans for verification of new features and execute them by creating new test cases requiring application of Design & DFT skills; Report bugs/enhancements in tool.

Collaborate with R&D and Product Engineering teams to review feature specifications, testplans & customer issues.

Debug issues reported by customers and suggest/implement measures to plug the gaps.

Position Requirements

B.E/B.Tech with 2+ years or M.E/MTech in Electronics/Electrical of experience

Strong in Digital electronics, Verilog

Good understanding of DFT techniques and methodologies

Familiarity with Test standards like 1149.1, 1500, 1687 is a plus

Experience with Cadence Test or other Test tools is preferred

Modus is a DFT (Design for Testability) software tool from Cadence used by leading chip design companies during DFT synthesis & ATPG (Automatic Test Pattern Generation) phase of chip design
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