Senior ARM RTL Design - Architect

Cadence Design Systems

4.4

Austin, TX

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refinement. Ability to work with verification/validation team to create performance verification plan

RTL development
Support Verification teams. Support test bench development, review verification and vPlans. Provide timely specification clarifications and debug support
Physical design deliverables. Create functional timing constraints, synthesize RTL to ensure power and area targets are met and constraints are correct
Plan development schedule in detail and track deliverables to ensure timely IP delivery to all consumers
Work with multi-disciplinary teams to ensure design block/IP success for all target specifications in Silicon

Qualifications:

10+ years of Front End design and/or verification.with a BS/MS Engineering or Computer Sciences

Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration

Expert in RTL design (Verilog), simulators debuggers

Hands on Experience in Synthesis, SDC creation and support PD and STA teams.

Hands on experience on CDC/RDC setup, cleanup and ownership.

Experience in C/C++ and/or Python (or scripting language)

Experience in driving results in multi-disciplinary organization

Desirable:

A Self-motivated person with good communication and design management skills

Experience with Cadence front end toolset

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