Senior Design Technology Co-Optimization (DTCO) Engineer

Cadence Design Systems

4.4

(53)

Austin, TX

Why you should apply for a job to Cadence Design Systems:

  • 4.4/5 in overall job satisfaction
  • 4.4/5 in supportive management
  • 87% say women are treated fairly and equally to men
  • 89% would recommend this company to other women
  • 87% say the CEO supports gender diversity
  • Ratings are based on anonymous reviews by Fairygodboss members.
  • Parental leave is available for both paternity and maternity
  • Flexible work options available
  • 88% of employees at Cadence say it is a great place to work compared to 57% of employees at a typical U.S.-based company.
  • #R49205

    Position summary

    ing with leading semiconductor companies such as Intel and Synopsys.

    • Excellent problem-solving skills and ability to work in a fast-paced environment.

    • Strong communication and collaboration skills.

    Preferred Qualifications:

    • Experience with FIVR, AMS Security IPs, GPIO, and other related technologies.

    • Familiarity with PDK evaluations and multiple DIP teams (Memory, UCiE, SerDes).

    • Ability to manage multiple projects and prioritize tasks effectively.

    We're doing work that matters. Help us solve what others can't.

    Why you should apply for a job to Cadence Design Systems:

  • 4.4/5 in overall job satisfaction
  • 4.4/5 in supportive management
  • 87% say women are treated fairly and equally to men
  • 89% would recommend this company to other women
  • 87% say the CEO supports gender diversity
  • Ratings are based on anonymous reviews by Fairygodboss members.
  • Parental leave is available for both paternity and maternity
  • Flexible work options available
  • 88% of employees at Cadence say it is a great place to work compared to 57% of employees at a typical U.S.-based company.