Senior Lead DFT Design Engineer

• Should possess intimate knowledge of DFT insertion flows

• Basic scan chain insertion using synthesis or other software tools

• Experience in compression scan insertion, LBIST and other scan technologies

• Intimate knowledge of memory build-in self-test (MBIST)

• Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals

• Debug and Analysis of failures to improve fault coverage

• Verification of ATPG testbenches and debugging root cause of simulation mis-compares

• Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687

• Knowledge of timing analysis and equivalency checks would be added bonus

• Ability to work in collaborative team environment

• Prior experience with Cadence tools and flows is highly desirable

• Should be able to finish DFT tasks independently

• Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems

• Ability to work with stakeholders across cross-functional teams - Architecture, Design, Internal and External Customers

• Self-driven and committed individual who can work in a fast-paced project environment

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The annual salary range for San Jose, CA is $ 138,600 to $257,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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