Senior Principal Functional Verification Engineer - Applied ML

perience in function verification (formal verification and/or simulation/UVM verification) and a passion for leveraging artificial intelligence to redefine the verification landscape. In this role, you will operate at the forefront of semiconductor design and AI innovation, utilizing advanced AI tools to architect, design, and validate the next generation of verification methodologies. You will collaborate closely with a highly skilled team of machine learning engineers experienced in training large language models at scale, as well as accomplished software engineers with proven expertise in product development and deployment. This person will to be part of the ChipStack AI Super Agent team in San Jose, CA - working on the world's first agentic AI platform that autonomously designs and verifies chips with up to 10× productivity gains. Cadence has been nominated as a Great Place to Work globally and in Brazil, and is also a Fortune 100 Best Companies to Work For.

Key Responsibilities

• Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM.

• Develop agentic AI solutions using LLMs and latest ML technologies to accelerate pre-silicon Design Verification process.

• Employ AI enhanced Electronic Design Automation (EDA) tools to improve and expedite both the design and verification lifecycles.

• Engage directly with customers to understand requirements and deliver innovative, practical verification strategies.

• Collaborate effectively with machine learning and software engineering teams to validate output correctness, efficiency, and quality.

• Maintain current knowledge of advancements in AI-powered hardware verification and actively participate in fostering internal knowledge growth.

Required Qualifications

• BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience

• Proven expertise of more than 3 years in at least one of the pre-silicon ASIC verification methodologies such as Formal, SV/UVM and/or OVM.

• Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools.

• Hands-on experience with industry standard EDA tools (e.g., Jasper, Xcelium, IMC).

• Strong programming skills in Verilog, System Verilog and Python

• Excellent communication skills and the ability to thrive in a team-oriented environment.

• Self-motivated, with a proactive approach to problem solving, continuous learning, and innovation.

• Exposure to LLMs and ML technologies like RAG, RFT, RL, and Agentic frameworks would be a plus.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique "One Cadence - One Team" culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other-every day.

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