Software Engineer II

cus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.

• The unique "One Cadence - One Team" culture promotes collaboration within and across teams to ensure customer success

• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests

• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other-every day.

Job Summary

In this job, you will be responsible for development of Formal Verification IPs in form of a Verilog design model and System Verilog Assertions for industry standard bus protocols.

This role offers front row access to the cutting-edge innovation happening in Formal Verification and an opportunity to master a variety of protocols.

Job Responsibilities : This Job involves development of the Assertion Based Verification IPs.

• Candidate will write the designs and assertions for the formal verification.

• A fair bit of automation and scripting language like Python/TCL required in this activity.

• Candidate will work as an individual contributor and be a team player and needs to coordinate with cross geographic teams.

Qualifications :

• BE/BTech/ME/MS/MTech in Electrical/Electronics

Experience and Technical Skills required

• 2+ years of experience in RTL design/Verification in case of BE/BTECH or Masters Degree with Internship.

• Knowledge of scripting languages & Flow development is a big plus.

• Must have excellent debugging skills and ability to separate out the critical issues from trivial ones.

• Knowledge of at least one industry standard protocol (for example AHB, AXI, CHI, PCIe etc).

• Good understanding of the verification environment and design verification methodology is required.

• Knowledge of at least one industry standard protocol (for example AHB, AXI, CHI, PCIe etc) is a MUST.

• Very strong RTL design and synthesis concepts is required.

• Must have excellent debugging skills and ability to separate out the critical issues from trivial ones.

• Strong verification concepts like understanding spec, creating test plans, adding coverage is required.

• Strong analytical and problem-solving skills required.

• Formal verification knowledge will be a plus.

• Candidate should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/verification problems using these tools.

• Knowledge of scripting languages & Flow development is a big plus.

Behavioral skills required :

• Must possess strong written, verbal and presentation skills.

• Candidate should have good communication skills.

• Ability to establish a close working relationship with both customer peers and management.

• Explore what's possible to get the job done, including creative use of unconventional solutions.

• Work effectively across functions and geographies.

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