#R54372
erilog coding, UVM methodology projects, testbench creation, Simulation and Debug areas.
Mandatory experience-exposure to low-power simulation and Functional safety simulation for at least 2 years
Ability to author, analyze, and debug scripts in languages such as Bash, Perl, Python, and TCL
Strong programming and HDL design and verification skills
Ability to quickly analyze verification environments and design complexity
The selected candidate will:
Excel at multitasking
Expect to engage in a mixture of activities - authoring content, learning new tools and methodologies, "being the expert," teaching and interacting with customers, and working with highly competent and experienced engineers.
Given clear goals, work independently to accomplish such goals
Have excellent written and verbal English communication skills
Be well experienced using multimedia authoring tools, including Microsoft PowerPoint, Microsoft Word, and Adobe Acrobat and Photoshop (or equivalent), and audio/video tools such as Camtasia and Sound Forge.
Be detail-oriented, well-organized, and receptive to challenges.
Proactively react to resolve issues impeding progress
We're doing work that matters. Help us solve what others can't.