Sr Principal Design Engineer

Cadence Design Systems

4.4

Bengaluru, India

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RTL and gate level (no-timing and timing) simulations to verify DFT functionality.

Work closely with Test Engineering for test program development and Silicon bring up, diagnosis, Yield improvement, etc.
Work closely with EDA RnD teams to propose and implement new features.

Requirements:

B. Tech /BE/ME/M Tech with 8-15+ years of relevant hands-on experience in Design for Test (DFT).
Clear understanding of key DFT concepts like Scan compression, Scan Stitching, fault models (stuck-at, delay tests, IDDQ, Small Delay, etc.), IEEE P1500, MBIST, IEEE 1149.1/6 (Boundary scan), IEEE 1687, etc.
Working knowledge of RTL coding in Verilog, Synthesis & STA
Experience in at least one scripting language like PERL, Python, TCL, or Shell is preferred.
Hands on experience with either Tessent/Modus ATPG tool
Proven success in development of complex custom ASIC products in advanced process nodes
Hands-on experienced and successful taped out several ASICs.
Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals.
Excellent written and verbal communication skills.

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