cycle processes to ensure product quality.
Job Requirements:
- The position requires MSEE, or equivalent, with a minimum of 5 years significant experience in designing complex protocols and/or hardware systems.
- MUST have excellent communication skills with both written and spoken English.
- Fluent and extensive RTL design knowledge using Verilog/SystemVerilog is required along with experience using RTL verification tools and flows.
- Must excel in and demonstrate solid debugging experience/skills.
- Emotionally intelligent collaborator and communicator. Experience with team-wide collaboration tools and processes.
- Drive and ability to schedule workload and plan own tasks effectively as well as coordinate with and adapt to other's needs and priorities when needful. Agile! Adaptive!
- Verification experience using Cadence simulation and/or emulation products is a PLUS.
- Programming experience with scripting languages like Perl, TCL, C-shell is a PLUS.
- Experience in memory sub-system design and operation is a PLUS.
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