Sr Principal Design Engineer- Memory IP

Cadence Design Systems

4.4

(53)

San Jose, CA

Why you should apply for a job to Cadence Design Systems:

Ranked as one of the Best Tech Companies for Women in 2022

4.4/5 in overall job satisfaction

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Parental leave is available for both paternity and maternity

Flexible work options available

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Position summary

l engineering, microelectronics, comparable engineering science or solid state physics.

Essential that the individual demonstrates strong communication, verbal and written.
Experience on the memory IP is desired
Requires good communication skills in English.

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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