Sr Principal Digital Verification Engineer

ports to:** Design Engineering Director

Job Overview:

The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) for a variety of High-Tech Markets. Our IP will be integrated into industry leading Chiplet subsystems. The Cadence IP and Chiplet based solutions allow our Customers to tackle their system level challenges, enabling them to focus on product differentiation and to reduce time to volume.

The Sr Principal Digital Verification Engineer will be based in Edinburgh as part of an experienced Chiplet Team, alongside established Controller development sites in Europe, US and India.

Job Responsibilities:

• Architecture of Verification Environments for complex IP such as Ethernet, CXL, Storage

• Development of UVM-SV Scoreboards for self-checking regressions

• Development of Functional Coverage as part of Metric Driven Verification Environments

• Development of SystemVerilog Assertions for use in Formal and Simulation Environments

• Definition and Management of Verification Plans (vPlans) using Cadence vManager tools

• Creation and Management of Automated Regression Environments, e.g. Jenkins

• Participation in Technical Review Meetings and Checklist Reviews as part of ISO-9001

• Close Collaboration with Design Engineers to debug complex test scenarios

Job Qualifications:

• Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline

• 15+ years' experience in microelectronics/EDA industry

• Experience of Verilog RTL Design essential

• Experience of Metric Driven Verification (MDV) essential

• Excellent oral and written English essential

• Self-motivated with excellent planning, interpersonal, and communication skills

Additional Skills/Preferences:

• Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred

Additional Information:

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

Travel: <5%

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