Staff Engineer -Gate Level Verification (SystemVerilog, UVM, and GLS).

aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, GLS and Formal techniques. Candidate will require close interactions with Design, SoC , Validation, Synthesis & PD teams for design convergence. Candidate must be able to take ownership of IP/Block/SS verification. He/She will work with design team (both HW and SW) on RTL debug during Pre-silicon HW development phase.

Responsibilities:

• Develop and execute verification plans using System Verilog and UVM to validate complex ASIC/FPGA designs.

• Design and implement testbenches and verification environments to ensure functional accuracy and performance.

• Perform Gate-Level Simulations (GLS) to validate designs against their RTL implementations.

• Create and run comprehensive verification scenarios and identify discrepancies between RTL and gate-level simulations.

• Collaborate with design engineers to understand requirements and resolve design issues.

• Debug and troubleshoot complex issues, providing detailed analysis and solutions.

• Document verification processes, methodologies, and results to ensure clarity and reproducibility.

• Participate in design reviews and contribute to improving verification strategies and methodologies.

• Verify and debug low-power design

• Debug SDF Back Annotated Gate Simulations

• Collaborate with cross-functional teams to define and execute gate-level simulation test plans.

• Develop and implement gate-level simulation strategies for complex digital designs.

• Conduct gate-level simulations to verify the functionality and performance of digital designs.

• Work closely with design and verification teams to identify and resolve issues at the gate level.

• Utilize your expertise in SV and UVM to optimize and enhance the gate-level simulation process.

• Ensure compliance with industry standards and best practices in gate-level simulation.

• Develop a comprehensive GLS methodology for the CPU

• Perform gate-level simulations to verify the functionality, performance, and timing of CPU designs.

• Develop and execute comprehensive test plans for gate-level simulations.

• Collaborate with RTL design, verification, and physical design teams to identify and resolve simulation issues.

• Analyze simulation results, debug failures, and propose design improvements.

• Ensure thorough coverage and validation of all critical paths and corner cases.

• Automate simulation workflows to enhance efficiency and reproducibility.

• Assist in the development and maintenance of simulation environments and tools.

• Document simulation methodologies, results, and best practices.

• Understanding of industry-standard protocols and interfaces

• Familiarity with static timing analysis (STA) and power analysis.

• Understanding of power domains and HW programming guide sequences

• Develop test plan to verify all low power states

• Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals

• Exploring innovative dynamic or static methodologies by engaging with EDA vendors

Experience Level: 10-15 years in Industry

Education Requirements: Bachelor or Master's degree in Electrical and/or Computer Engineering

Minimum Qualifications:

• 10+ years of professional experience in ASIC/FPGA verification with strong expertise in SystemVerilog, UVM, and Gate-Level Simulation (GLS).

• Proven experience in developing and executing testbenches and verification environments.

• Strong skills in performing gate-level simulations and analyzing results.

• Excellent debugging skills with the ability to resolve complex design issues.

• Effective communication and collaboration skills, capable of working well in a team environment.

• Analytical debugging skills

• Verify and debug low-power design

• Debug SDF Back Annotated Gate Simulations

• Low-power implementation (UPF)

• Mixed Signal Real Number Modeling (RNM, Spice)

• Strong System Verilog/UVM based verification skills Experience with Assertion coverage-based verification methodology

• Experience in formal / static verification methodologies will be a plus

• Good understanding of low power design techniques

• Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells.

• Experience with UPF/CPF based power aware verification.

• Experience with Synopsys NLP (native Low Power) tool.

• Working knowledge of GLS , PAGLS and scripting languages such as Perl, Python is a plus

• Proficiency in Low-Power standards like UPF/CPF.

• Working knowledge on UPF based RTL / PGPIN simulations.

• Proficiency in ASIC design tools, simulation methodologies, and hardware description languages (HDLs).

• Excellent analytical and problem-solving skills with a focus on power optimization

Preferred Qualifications:

• Mentoring skills

• Exceptional problem-solving skills

• Good written and oral communication skills

Benefits & Perks : Not only will you be joining a highly skilled and tight-knit team where every engineer makes a significant impact on the product; we also strive for good work/life balance and to make our environment welcoming and fun.

• Equity Rewards (RSUs)

• Employee Stock Purchase Plan (ESPP)

• Insurance plans with Outpatient cover

• National Pension Scheme (NPS)

• Flexible work policy

• Childcare support

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.