Staff Verification Engineer

g and digital peripherals, advanced security, advanced power management, and best in class low power wireless modems. We strive to provide advanced technology solutions through innovation in custom RISC-V Cores and AI/ML accelerators.

Staff Verification Engineer
The position involves executing a verification plan on digital IP blocks using a combination of simulation and formal verification techniques. The qualified candidate should have built UVM test benches from scratch and taken them through all stages of execution. The candidate will interact with cross-functional teams to receive specs, create, and execute verification plans, and debug IP and system-level issues. Based on the project needs the candidate will debug chip level tests for functionality, power, and performance.

Responsibilities

• Block and IP Verification

• Create and execute the test plan with emphasis on metrics driven verification

• Constrained random tests, scoreboard, and coverage development

• Validate block power and performance requirements

• Apply formal verification tools like lint, auto, and property checks

• System Level Verification

• Debug functional failures at subsystem and SoC levels

• Perform gate-level verification across corners and provide activity files for power analysis

• Flows and Methodology

• Architect and implement Verification Components using UVM-based methods

• Develop verification flows and methodologies to enhance IP, SoC, and Formal Verification

Skills You Will Need:

• 12+ years in Industry

• Bachelor's or Master's degree in Electrical/Computer Engineering

• Strong knowledge of Verilog, SystemVerilog, UVM, and C/C++

• Knowledge of digital design, ARM, or RISC-V architecture and bus protocols

• Knowledge of scripting languages like Perl, Python, Tcl, and shell

• Advanced verification skill in SVAs, constrained random stimulus, and coverage analysis

• C-based testcase development and debugging skills

The following qualifications will be considered a plus:

• Verify and debug low-power design with UPF

• Debug SDF Back Annotated Gate Simulations

• Mentoring and leadership skills

• Exceptional problem-solving skills

• Good written and oral communication skills

Benefits & Perks

You can look forward to the following benefits:

• Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental and vision plans

• Highly competitive salary

• 401k plan with match and Roth plan option

• Equity rewards (RSUs)

• Employee Stock Purchase Plan (ESPP)

• Life/AD&D and disability coverage

• Flexible spending accounts

• Adoption assistance

• Back-Up childcare

• Additional benefit options (Commuter benefits, Legal benefits, Pet insurance)

• Flexible PTO schedule

• 3 paid volunteer days per year

• Charitable contribution match

• Tuition reimbursement

• Free downtown parking

• Onsite gym

• Monthly wellness offerings

• Free snacks

• Monthly company updates with our CEO

#LI-KB1

#LI-Hybrid

The annualized base pay range for this role is expected to be between $0 - $0 USD. Actual base pay could vary based on factors including but not limited to experience, geographic location where work will be performed and applicant's skill set. The base pay is just one component of the total compensation package for employees. Other rewards may include an annual cash bonus, equity package and a comprehensive benefits package.

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.