#420316-en 1
Verilog, SystemVerilog, digital microarchitecture)
BS plus 7 years relevant experience. MS preferred
Experience in breaking down the digital signal processing algorithms into Micro/RTL architecture while making cost and quality trade-offs
Experience in coding C/C++/Python/Bash
Experience with High Level Synthesis for ASICs or FPGAs is an add-on
Knowledge of basic processor architecture
Experience with full ASIC design cycle (spec through bring-up) preferred
#LI-EDA
#Hybrid