#437651-en 1
stbenches composed of embedded software and hardware components on platforms such as Questa or Veloce.
Job Requirements:
B.Sc. or M.Sc. in Computer, Electronics, or Communication Engineering.
Proven experience in H/W design verification.
Expertise in SystemVerilog for creating testbenches and writing assertions.
Proficient in UVM (Universal Verification Methodology) for building reusable verification environments.
Strong understanding of code coverage and functional coverage techniques.
Experience with integrating commercial VIP into UVM testbenches.
Solid knowledge of RTL development and Verilog.
Strong understanding of digital circuits, design, and computer architecture.
Familiarity with Siemens EDA tools and solutions.
Knowledge of C, C++, and object-oriented programming.
Proficiency in scripting languages (Perl, Shell, TCL).
Excellent command of the English language, with strong presentation and communication skills.
Ability to work independently and collaboratively in a team environment.
Knowledge of storage protocol standards (UFS, USB, SAS, SATA, etc.) is a plus.
Experience with SystemC programming is a plus.
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We offer a comprehensive reward package which includes a competitive basic salary, bonus scheme and generous holiday allowance.
Siemens is an equal opportunities employer and do not discriminate unlawfully on any grounds. We are committed to providing access and equal opportunity.
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