Technology Enablement Engineer(Tessent)

foundries on a wide range of joint projects and the goal is to enable the ecosystem for the industry.

We provide technical supports for the joint foundry/fabless working model with focusing on silicon learning like scan diagnosis, memory diagnosis and diagnosis driven yield learning. At the meantime we depth technical including new methodology development, solution validation, reference flow build-up, technical documentation write-up and success story publication. The technical development involves every aspect of Tessent solutions and their applications in the sophisticated IC silicon life cycle.

Align with field account team to help resolve and understand priorities and develop a reproducible technical success to help achieve the goal by support business includes technical presentations and product demonstrations to a range of audiences, from users to decision makers; support evaluations, pre-sales training, and driven benchmarking.

• Availability for on-site time at the customers and partners and interacting with them for different technical areas and depth.

• Identify current and emerging technology challenges and connect these challenges with current Tessent technical solutions and product roadmap.

• Build product direction by collecting and prioritizing customer/partner requirements and providing usage scenarios. Drive market feedback to product development and marketing teams to evolve the next generation of methodologies and solutions.

• Lead beta programs, support beta partners and drive broad Tessent product adoption at target partners.

JOB QUALIFICATIONS

• Education of MS EE is desirable or equivalent &above.

• Consolidated experiences in silicon learning including 1st silicon debug on scan designs and scan diagnosis driven yield analysis.

• Product engineering experience for integrated circuit and that includes scan diagnosis data preparation, running diagnosis, cross domain analysis using scan diagnosis data with 10+ years of related practicing experience • and other physical or process data, helping drive failure analysis efficiency.

• Validated experience in ATPG, BIST, test compression, hierarchical-DFT, 3D IC, chain diagnosis, scan diagnosis, layout aware diagnosis, cell-aware diagnosis and BIST diagnosis. Tessent tools user would be preferred.

• Shown IC manufacturing process related knowledge and failure analysis experience such as defect root cause, mechanism and electrical behavior is needed.

• User of TCL/TK.

• Other knowledges like physical design, layout pattern analysis, DRC, and DFM rules could be helpful.

• Motivation of building outstanding unions and collaborate customers interactively.

• Excellent interpersonal skill with logical thinking and proficiency in written and verbal of English and Mandarin.

• Business travels to regional and international are required.
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We offer a comprehensive reward package which includes a competitive basic salary, bonus scheme, generous holiday allowance, pension, and private healthcare.

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