CAD Engineer - PDV

, you will be collaborating with the custom digital/analog/mixed-signal design, physical design (PD) and chip integration teams. With good understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, you will develop rule decks from scratch and/or modify existing ones. You will also have opportunities to develop ML/LLM based automations and solutions.

Description

-Develop, improve and maintain various aspects of physical verification flow and methodology

-Coordinate the effort of validating flows, improving for custom checks and data generation

-Work with the design and PD teams to facilitate the chip design process

-Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs

-Collaborate with tool vendors and foundries for PDK performance enhancements

Preferred Qualifications

Knowledge in Silicon chip design flows

DRC/LVS knowledge from previous work experience or coursework

Scripting experience in programming languages such as Python, Perl or Tcl

Experience with automation and development

Knowledge of ML/LLM is a plus

Minimum Qualifications

Minimum requirement of BS with 0 years of experience.

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