CPU Cache Microarchitect/RTL Engineer

ache subsystem architecture and RTL development for multi-processor systems.

Description

As a CPU Cache Microarchitect/RTL Engineer, you will own or participate in the following:
• Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification
• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals
• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification
• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance
• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power

Preferred Qualifications

Expertise in one or more of the following areas: coherence protocols and interconnects, high performance (low latency, high bandwidth) design techniques, memory subsystem queuing, scheduling, starvation and deadlock avoidance, SRAM design basics, multiple clock/power domains and power management strategies, prefetchers, replacement policies, debug capabilities, DFT strategies, error detection and correction

Understanding of low power microarchitecture techniques

Understanding of high-performance techniques and trade-offs in a CPU microarchitecture

Experience in C or C++ programming

Experience using an interpretive language such as Perl or Python

Minimum Qualifications

Minimum BS and 10+ years of relevant industry experience

Experience with microprocessor architecture

Experience with logic design principles with timing and power implications

Experience in Verilog or VHDL

Experience with simulators and waveform debugging process

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