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ork extensively with micro architects to help define the CPU and memory subsystem and performing feasibility experiments. Responsibilities also include but are not limited to: - Making area/frequency/performance/power trade-offs - Driving RTL-to-GDS flow through synthesis/place-and-route with ambitious goals for power, performance, and area - Working with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, power, testability, and reliability - Performing different floor planning experiments to understand the micro architectural feasibility for achieving high targets for performance, power and area - Performing different feasibility experiments for RTL innovations and improvements that drive the next generation high-performance and low power chips
Minimum Qualifications
Key Qualifications
Minimum BS
Physical Design Understanding and/or Experience
Logic Design fundamentals
Basic CPU microarchitecture understanding
Education & Experience
Minimum BS
Additional Requirements
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