Debug SoC Design Engineer

oC architects and IP developers to define debug features that meet the power, performance, and area goals.

You will own the design for the debug and trace hub. You will collaborate with other designers to ensure their subsystems implement the necessary debug features. You will guide validation engineers in the use of such features to diagnose issues. This is a highly visible role, where you will be at the center of the ASIC debug efforts, collaborating with all fields, with a critical impact in getting leading-edge products launched to delight millions of customers.","responsibilities":"RTL ownership of debug and trace hub - development, assessment, and refinement of RTL design to target power, performance, area and timing goals.

Micro-architecture development and specification - Work with a cross-functional team of silicon and software experts to explore and define architectural debug features, develop micro-architectural details, and arrive at a detailed specification.

Verification - support the verification team in test bench development and simulation/emulation for functional verification of debug features.

Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or overconsumption.

Validation - Aid in debug of silicon issues at SoC level by employing the necessary debug features

Collaboration with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process.

Preferred Qualifications

Knowledge and understanding of microprocessor debug such as CoreSight and other debug techniques.

Shown experience writing micro-architecture specifications and converting them to design.

Experience with AXI/AHB bus fabric and processor sub-systems.

Understanding of UPF and low-power design & implementation techniques.

Self-starter and willingness to learn.

Minimum Qualifications

BS with 3+ years relevant experience.

Familiarity with the ASIC design flow.

Knowledge of digital design, SoC architecture, and HDL languages like Verilog.

Familiarity with design methodologies and industry standard EDA tools.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $139,500 and $258,100, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.