Design Verification Engineer

itecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test effectively. You develop test plans, tests & coverage plans as well as define our next generation verification methodology & testbenches. You will actively communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases.

The SOC contains many subsystems and IP, so you may be working on one or several of the following types of IP:

• Neural Engine hardware

• DRAM subsystem, memory controller logic

• Encode and Decode systems for ProRes and other codec formats such as VP9, AV1

• Hardware security, including cryptographic algorithm implementations

• High-Speed IO standards such as PCI Express, DisplayPort, MIPI

• Power management and fabric infrastructure

• Memory cache management

• Display Subsystem for variety of panels and products

These are just some examples of the exciting designs that are part of our team. Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a collection of subsystems. It's up to you!

Preferred Qualifications

Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy

Knowledge of SystemVerilog, digital simulation and debug

Knowledge of computer architecture and digital design fundamentals

Good SW programming skills with knowledge of data structures and algorithms

Experience with Python, Perl, or similar scripting language

Ability to work independently to deliver the project goals

Knowledge of verification methodologies like UVM

Experience with C/C++, assembly is a plus

Excellent interpersonal and communication skills and the dream to take on diverse challenges

Minimum Qualifications

Minimum of BS + 10 years relevant industry experience.

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