Emulation Verification Engineer (Japan Design Center)

ou will be at the center of a chip design effort collaborating with all subject areas.

Are you ready to help us deliver the next groundbreaking Apple products?

Description
As a member of Emulation verification team, you will play a key role in using Emulation for verification of mixed signal SoCs which has large digital and analog sections. The individual will be responsible for porting the design to Emulation platform with the help of the Emulation team and then delivering the verification plan.","responsibilities":"Bringing up the emulation platform for mixed signal SoCs
Developing monitors and checkers for Emulation platform and come up with the latest techniques to achieve better performance
Preparing and delivering the test plan and performing reviews with the cross functional teams
Collaborating cross functionally with Design, Architecture, Power, Silicon Validation, Performance and SW Teams
Developing code for Design and verification that aids with emulation activities, using Verilog/System Verilog/UVM

Preferred Qualifications
Experience with System Verilog verification environments including C/C++ DPI, UVM
Understanding of the tool flow from RTL to Emulation
Experience in UVM Acceleration

Minimum Qualifications
Over 5 years of experience with bring up, debugging and verification in Emulation
Good understanding of any Standard Emulator (Palladium, Veloce, Zebu) OR FPGA (Xilinx, Altera) flow
Proven design verification skills
Experience in writing Synthesize-able System Verilog/Verilog code and System Verilog assertions
Experience on any Scripting (Perl/Python/TCL)
Excellent analytical and debug skills
Excellent oral and written English skills

Apple is an equal opportunity employer that is committed to inclusion and diversity, and thus we treat all applicants fairly and equally. Apple is committed to working with and providing reasonable accommodation to applicants with physical and mental disabilities.