Formal Verification Framework for Hardware IPs Validation

well as some knowledge in hardware modeling. The intern will work on developing comprehensive property sets to achieve functional coverage of hardware models. The focus will be on formalizing properties in SVA and executing formal proofs using industry-standard tools. A key challenge will be identifying optimal trade-offs between model accuracy and proof convergence times. The intern will then extend the verification framework in order to integrate the properties at higher levels to enable system verification.

Responsibilities

• Define comprehensive property sets for functional coverage of hardware models.

• Formalize verification properties using SVA.

• Execute formal proofs and analyze convergence behavior (accuracy VS execution time)

• Document methodology and best practices for the verification flow.

Minimum Qualifications

• Currently enrolled in a Master's degree in Computer Science or equivalent

• Knowledge of formal verification techniques

• Knowledge of Verilog and/or VHDL

• Passionate about mathematics

• Scripting language knowledge (perl/python)

• Good written and verbal communication skills

• Experience in working with international teams

• You are available for 6 months or more

Preferred Qualifications

• Bachelor in Computer Science or equivalent

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