#200586882-0157_rxr-8
Ensure implementation readiness with RTL lint and custom checks. - Automate front-end design integration process. - Understand specifications for design units. - Collaborate with cross functional teams.
Minimum Qualifications
BS required.
Experience with Verilog/System Verilog.
Preferred Qualifications
Experience with logic design principles.
Experience with RTL analysis using Invio or other tools.
Knowledge of synthesis, PNR and STA tools and flows.
Familiarity with GPU/CPU/SIMD Architecture and micro-architecture.
Ability to work well in a team and be productive under aggressive schedules
Relevant coursework in computer architecture, digital logic design and VLSI design.
Proficiency in programming techniques and scripting languages (Perl/Ruby/Python).
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