Mixed-Signal Clocking and Control RTL Design Engineer

ents and jitter. You will work closely with static timing experts for timing closure and front-end quality tools such as Lint/CDC/RDC. You will work with system architects to determine implementation of new designs, and with design verification teams to craft/debug tests. You will also contribute to post-silicon debug and analysis of these designs.

Preferred Qualifications

Excellent knowledge of digital logic gates, clocking and state elements

Excellent knowledge of writing synthesizable code in SystemVerilog

Solid understanding of logic and behavioral simulations, and working knowledge of STA/Lint/CDC/RDC tools

Solid understanding of clocking fundamentals such as jitter, phase and frequency modulation

Good understanding of various phase and frequency detectors, oscillators, delays line and phase interpolators

Prior experience working on clocking circuits such as PLLs/DLLs/CDRs

Familiarity with DACs and oversampling modulators

Familiarity with SERDES clocking and Equalization, line coding schemes and multi-level signaling

Familiarity with the basics of digital signal processing and closed loop control

Minimum Qualifications

MS degree in technical discipline with minimum of 3 years of relevant experience.

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