#200591952-6109_rxr-662
echnology.
Preferred Qualifications
Knowledge in Verilog - advantage
Minimum Qualifications
3+ years of experience in physical design of large-scale SoCs
B.Sc / M.Sc Electric Engineering / Computer Engineering
Extensive experience with one of the place & route tools (Synopsys / Cadence)
Scripting and Programming experience using either TCL or Python or Perl, or known Shell scripting languages","internalDetails":null,"eeoContent":null