#200573052_EN
art time, number of days, how many days per week - will be flexibly configured considering selected intern's availability and preference.
Description
Specific project and assignment will be tailored to individual intern based on his /her interest, strength and background. Some general responsibilities may include: - Engage in new concept, methodology and features in the DV community. - Evaluate CAD tools and adopt them for production use - Help debug design verification issues and resolve them - Creating scripts to enhance existing system for design verification work.
Pursuing a BS, MS, or Ph.D. in domains of: Electrical Engineering, Computer Science or Applied Physics.
Holding relevant work permit in Japan for the duration of the internship. No immigration support will be available for this internship.
Interest in Mixed-Signal LSI design , digital design or verification - passion to innovate things with your own hands.
Have experiences working with Verilog or System Verilog.
Preferred Qualifications