#55969421AF63B892794679504E6FE952-26279f
nism. - Select appropriate FPGA families and IP for timing-critical and safety-related functions.
Develop synthesizable RTL (VHDL) for:
Implement:
Develop testbenches and simulations to verify:
Perform static timing analysis and timing closure for:
Support lab and field testing:
Create and maintain documentation:
Support production and field updates (JTAG, in-system programming, secure and fail-safe update mechanisms).
Your Profile:
Bachelor's or Master's degree in Electrical Engineering, Information Technology, Computer Engineering, or a related field, with a focus on FPGA or digital hardware design.
Several years of professional experience in FPGA design, preferably in real-time, control, or power electronics applications.
Strong proficiency in VHDL and a solid understanding of synthesizable RTL design, timing constraints, and clock domain crossing techniques.
Hands-on experience with at least one major FPGA vendor toolchain.
Experience with time-critical logic such as PWM generation, high-resolution timers, or communication interfaces.
Fluency in English is required; German is a plus.
Key Competencies:
Strong problem- solving skills in time-critical and safety-related systems.
High attention to detail, especially regarding timing, jitter, and protection logic.
Ability to collaborate with control, power electronics, hardware, and firmware teams.
Clear communication of complex timing and architecture decisions.
We****offer:
Company bound by a collective bargaining agreement with 35 hours/week and 30 days of vacation
Flexible working time arrangements
On-site canteen in Berlin
Welcome Days for the perfect start in a global company
Additional Information
Relocation Assistance Provided: No