Silicon RTL Design Lead, Google Cloud

tion. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will contribute in all phases of application-specific integrated circuit (ASIC) designs from design specification to production. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver quality designs for next generation data center solutions.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Lead a team of Engineers in the Bangalore design organization to deliver complex IPs or Subsystems.Communicate and work with multi-disciplined and multi-site teams.
• Define uArch specifications and block level design documents containing interface protocol, block diagram, transaction flow, pipeline, etc.
• Perform RTL development, subsystem and SoC Integration and Lint/CDC/FV/UPF checks.
• Participate in simulation debugs, synthesis, timing/power closure, and silicon bring-up.
• Participate in test plan and coverage analysis of the block and SOC-level verification.